All of the current Alpha CPUs use high-speed clocks, because their
microarchitectures have been designed as so-called short-tick
designs. None of the sytem busses have to run at horrendous speeds as
a result though:
on the 21066(A), 21064(A), 21164 the off-chip cache (Bcache)
timing is completely programmable, to the resolution of the CPU
clock. For example, on a 275MHz CPU, the Bcache read access time can
be controller with a resolution of 3.6ns
on the 21066(A), the DRAM timing is completely programmable, to
the resolution of the CPU clock (not the PCI clock, the CPU clock).
on the 21064(A), 21164(A), the system bus frequency is a
sub-multiple of the CPU clock frequency. Most of the 21064
motherboards use a 33MHz system bus clock.
Systems that use the 21066 can run the PCI at any frequency
relative to the CPU. Generally, the PCI runs at 33MHz.
Systems that use the APECs chipset (see Section
The chip-sets
) always have their CPU system bus equal to their PCI bus
frequency. This means that both busses tends to run at either 25MHz or
33MHz (since these are the frequencies that scale up to match the CPU
frequencies). On APECs systems, the DRAM controller timings are
software programmable in terms of the CPU system bus frequency
Aside: someone suggested that they were getting bad performance
on a 21066 because the 21066 memory controller was only running at
33MHz. Actually, it's the superfast 21064A systems that have memory
controllers that 'only' run at 33MHz.
